ARM
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[edit] ARM Architectural Highlights
- Load/Store
- Very small yet high-performance
- Simple addressing modes
- Auto-increment/decrement to efficiently support loops
- Load and Store Multiple instructions to maximize data throughput
- Conditional execution of instructions to maximize execution throughput
[edit] Registers
- 31 GPRS (32-bit)
- 16 user-visible
- 16 used to speed up exception processing
- Two of 16 user visible registers have a special role
- R14: Link Register (LR) holds address of next. instr. after BL (Branch and Link). BL is used for subroutine calls
- R15: Program Counter (PC)
- Software normally used R13 as SP (Stack Pointer) register
[edit] Exception types
Five exceptions with a privilege mode for each type
- fast interrupt
- normal interrupt
- memory aborts (used to implement memory protection)
- attempted execution of undefined instruction
- software interrupt (SWI) instructions
[edit] Exception processing
- On exception, some of the standard registers are replaced with registers specific to the exception mode.
- All exception modes have replacement banked registers for R13 and R14
- Fast interrupt mode has more registers for faster processing
- R14 is used to hold address on next intruction to return to after exception processing
- R13 is banked across exception modes to provide each ex. handler with private stack pointer
- Fast interrupt mode also banks R8 - R12 so fast interrupt processing can begin without need to save / restore these registers
Sixth privilege mode is System mode. It uses user-mode registers.
[edit] Other Registers (Status Registers)
- CPSR - Current Program Status Register (Condition codes, interrupt enable/disable, processor mode, ARM/Thumb mode)
- SPSR - Saved Program Status Register : Copy of CPSR before exception has occurred.
[edit] Instructions
- Branch
- Data Processing
- Status register transfer
- Load & Store
- Coprocessor
- Exception-generating
[edit] Load and Store Multiple Registers (LDM & STM)
Perform block transfer of any number of GPRs to or from memory. Four addressing modes are provided
- pre-increment
- post-increment
- pre-decrement
- post-decrement
Base address is specified by a register value, which can be optionally updated after the transfer. Subroutine return address and PC are in GPRs. As a result, very efficient subroutine entry and exist sequences can be contructed with LDM & STM:
- Single STM at subroutine entry can push register contents and the return address on stack, updating stack pointer in the process
- Single LDM at subroutine exit can pop register contents from the stack with return address, and update the stack pointer
(pp 87, ARM architecture Reference Manual)
LDM{<cond>}<addressing_mode> Rn{!}, <registers>{^}
STM{<cond>}<addressing_mode> Rn{!}, <registers>{^}
! - Set the W bit, causing instruction to write modified value back to base register Rn addressing_mode = IA, IB, DA, DB, FD, FA, ED, EA
- IA - Increment After
- IB - Increment Before
- DA - Decrement After
- DB - Decrement Before
Following four modes are more appropriate for stack operations:
- FA - Full Ascending
- FD - Full Descending
- EA - Empty Ascending
- ED - Empty Descending
- Full Stacks - Have SP that points to last full location
- Empty Stacks - Have SP that points to first empty (unused) location
- Descending Stacks - Grow towards decreasing memory addresses
- Ascending Stacks - Grow towards decreasing memory addresses
[edit] Examples
STMFD R13!, {R0 - R12, LR}
Saves Registers in range R0 to R12 and LR (R14) in Full Stack Descending fashion. Updates Stack Pointer in the end
LDMFD R13!, {R0 - R12, PC}
Register Registers in range R0 to R12 and PC (R15) in Full Stack Descending fashion. Updates Stack Pointer in the end
